AMD Launches EPYC 'Venice': The First x86 Server CPU Built on TSMC's 2nm Process
AMD's Zen 6 EPYC Venice debuted at Advancing AI 2026 with up to 256 cores and 70% higher performance-per-watt than its predecessor. It's the commercial first for 2nm server silicon.
AMD launched EPYC “Venice” at its Advancing AI 2026 event in San Francisco on July 22, marking the commercial debut of the first x86 server CPU built on TSMC’s 2nm Gate-All-Around process.
The flagship configuration scales to 256 Zen 6 cores — a 33% jump over the 192-core EPYC “Turin” lineup it replaces. AMD claims over 70% higher performance and efficiency than the Zen 5 generation, driven partly by the node shrink and partly by a redesigned I/O architecture. Venice moves to a new SP7 socket with 16-channel memory support, delivering up to 1.6 TB/s of memory bandwidth, and adds PCIe Gen 6 for faster attached storage and networking.
CEO Lisa Su used the two-day keynote to lay out AMD’s full-stack AI pitch: Venice CPUs paired with the new Instinct MI450-series GPU accelerators inside Helios rack systems carrying 31 TB of HBM4 per rack. The pitch is a complete, vertically-designed AI compute platform — CPU, GPU, memory, and interconnect shipping as one system rather than components buyers stitch together themselves.
Venice’s 2nm milestone matters beyond the spec sheet. TSMC’s N2 node has been running in mobile and client silicon, but a 256-core server part is a different manufacturing challenge — yield, power delivery, and thermal density at that transistor count are unforgiving. AMD getting there first on the server side, ahead of Intel’s competing 18A roadmap, is a real manufacturing win, not just a marketing one.
For buyers, the immediate calculus is straightforward: more cores per socket means fewer sockets per rack for the same throughput, which matters directly for power and cooling budgets in AI-adjacent data centers where every watt is contested between CPU and GPU. The 16-channel memory jump also matters for memory-bound workloads — inference serving, in-memory databases, and the CPU-side preprocessing that feeds GPU clusters.
AMD didn’t put a specific general-availability date on Venice beyond confirming a second-half 2026 ship window for Helios racks pairing it with MI450X accelerators. Expect the first hyperscaler deployments before broader OEM availability, following the pattern set by prior EPYC generations.