AMD EPYC Venice (Zen 6, 256 Cores) Enters Volume Production on TSMC 2nm — First HPC CPU at This Node
AMD's 6th-gen EPYC server processor is now in volume production at TSMC's 2nm fab, making it the first high-performance computing CPU at this node. Venice claims over 70% performance-per-watt improvement and 30% more thread density versus the current EPYC Turin generation.
AMD confirmed on May 21, 2026 that its sixth-generation EPYC processor — codenamed “Venice” and built on the Zen 6 microarchitecture — is now in volume production at TSMC’s N2 (2nm-class) fabrication facility in Taiwan. It is the first high-performance computing CPU to enter mass production at this node. A second production ramp at TSMC’s Arizona facility will follow later in 2026.
Venice ships in configurations up to 256 cores per socket. AMD claims more than 70% improvement in performance-per-watt over EPYC Turin (Zen 5) and more than 30% increase in thread density on the same socket footprint.
What Zen 6 on N2 means for data centers
The jump from TSMC N3 (used in Turin) to N2 is not incremental. TSMC’s N2 process uses gate-all-around nanosheet transistors, replacing the FinFET design that defined the past decade of processor manufacturing. Gate-all-around transistors wrap the gate material on all four sides of the channel, reducing current leakage and enabling tighter packing at the same voltage headroom.
Practical effect for Venice: AMD can fit 256 fully functional cores on a multi-chiplet die stack while keeping TDP at a level that existing 400W OCP and AMD server socket specifications can handle. The previous record for a server CPU was AMD’s EPYC Turin at 192 cores.
Performance-per-watt over raw frequency
AMD’s messaging for Venice is deliberately centered on efficiency, not clock speed. The company is targeting hyperscalers and cloud providers whose infrastructure cost is dominated by power and cooling, not purchase price. A 70% efficiency gain across a 100,000-node cluster translates directly to measurable reductions in electricity spend and cooling capacity.
Intel’s competing Clearwater Forest (Xeon 6 on Intel 18A) is also expected in 2026, though Intel has not confirmed volume production dates. NVIDIA’s Grace CPU Superchip, used in GB200 NVL72 racks, targets AI workloads specifically and is not a direct server-general competitor.
Availability and ecosystem
Venice will slot into the same SP5 (LGA-6096) socket as Turin, enabling server OEMs to upgrade existing platforms with a firmware update rather than a full chassis redesign. Dell, HPE, Lenovo, and Supermicro have all confirmed Venice-compatible server lines.
General availability for Venice-based servers is expected in Q3 2026. Cloud instances on AWS, Google Cloud, and Azure typically follow 3-6 months after GA hardware availability — so Venice-backed instances are likely by Q4 2026 or Q1 2027.
AMD’s data center revenue has grown sequentially for seven consecutive quarters. Venice is the bet that momentum continues through an increasingly competitive server CPU landscape.