AMD EPYC Venice Becomes First HPC Silicon on TSMC N2 — Zen 6 at 2nm With Arizona Production Confirmed
AMD confirmed EPYC Venice (Zen 6) is the first HPC product taped out on TSMC's 2nm-class N2 process, delivering a 10-15% performance uplift over Turin. Simultaneously, AMD confirmed EPYC 9005 volume production at TSMC's Arizona Fab 21, satisfying US CHIPS Act provenance requirements.
AMD confirmed that EPYC “Venice” — its next-generation server CPU on the Zen 6 architecture — is the first high-performance computing product taped out on TSMC’s N2 process node. N2 is TSMC’s 2nm-class technology, and Venice is the leading edge of AMD’s server roadmap for 2027 and beyond. AMD disclosed the milestone alongside confirmation that current 5th-gen EPYC 9005 “Turin” processors are validated for volume production at TSMC’s Fab 21 in Phoenix, Arizona.
The N2 process delivers 10-15% single-threaded performance improvement at equivalent power, or 25-30% power reduction at equivalent performance, versus N3E (the node used for Turin). TSMC’s Arizona Fab 21 has reached approximately 70% yield rates on N2 silicon — the threshold considered commercially viable for large-scale production. Volume output is expected before the end of 2026.
Why the Arizona Announcement Is as Important as N2
US export control policy has pushed hyperscalers and enterprise customers to demand geographically verified, non-Chinese-fab supply chains for AI and server infrastructure. AMD confirming domestic EPYC 9005 production removes a procurement obstacle that had slowed large-scale EPYC deployments in Azure, AWS, and Google Cloud’s regulated workloads. Server silicon built at TSMC Arizona satisfies CHIPS Act provenance requirements for US government and defense procurement.
TSMC’s Fab 21 in Phoenix is currently the only high-volume TSMC production facility outside Taiwan. Phase 2 (N2) production begins in 2026. Phase 3 (A16) is scheduled for 2028. The total Arizona investment now exceeds $65 billion — one of the largest semiconductor manufacturing commitments in US history.
The Intel Competitive Angle
Intel unveiled Clearwater Forest Xeon (Nova Lake, 52 cores) on its 18A process at COMPUTEX this week. Two distinct sub-3nm paths are now confirmed: AMD on TSMC N2, Intel on Intel 18A. These nodes are not directly comparable — TSMC N2 and Intel 18A have different transistor architectures, power characteristics, and density profiles — but both represent the cutting edge of what’s commercially achievable in 2026.
AMD has historically outperformed Intel when it maintains a process lead. If TSMC N2 Venice holds its yield advantage through production ramp, the 10-15% IPC gain compounded with frequency headroom gives AMD a credible argument in the hyperscaler RFP market against Nova Lake.
Venice core counts and clock speeds have not been disclosed. Tape-out confirmation in the server market typically precedes production silicon announcements by 18 months, placing Venice in production for calendar year 2028 server deployments.
GPU Timeline Still Open
AMD has not confirmed when RDNA 5 discrete GPUs or Instinct MI400 AI accelerators will move to TSMC N2. The Venice tape-out does confirm that AMD’s N2 allocation from TSMC is substantial enough to run a full server CPU program — the allocation question for Instinct MI400 vs. NVIDIA Blackwell Ultra remains the more commercially critical one for AI infrastructure buyers.
For data center architects planning AI accelerator procurement for 2027-2028, the Venice N2 confirmation is a signal, not a commitment. Watch for AMD’s Instinct roadmap update at its Data Center and AI Technology Premiere later this year.